The present invention relates to a semiconductor device for flip-chip connections and to a technique for manufacturing the same. More particularly, the present invention relates to a technique that is effective when applied to a semiconductor device and a manufacturing method using the technique known as xe2x80x9cwafer level packagingxe2x80x9d, in which a packaging process is performed at one time in the wafer state on a plurality of semiconductor chips formed in a semiconductor wafer via a wafer process.
According to an investigation performed by the present inventor, the following techniques may be considered with respect to semiconductor devices and semiconductor device manufacturing methods. Generally, most semiconductor devices have laminated structures, and, in most cases, insulating layers are disposed between the respective layers of such semiconductor devices. Opening parts are formed in these insulating layers, and wiring, which connects the terminals of the upper layers and the terminals of the lower layers, is formed so that this wiring passes through these opening parts.
The following method is used to form the abovementioned insulating layers. Specifically, the semiconductor device is coated with a photosensitive insulating material by a spin-coating process, and opening parts are formed in the insulating layer by performing exposure and development. Furthermore, in regard to the metal wiring that connects the terminals of the lower layers and the terminals of the upper layers, the surface of each insulating layers coated with a second photosensitive material, and a mask is formed by subjecting this material to exposure and development; then, metal wiring, which connects the terminals of the layer beneath the insulating layer and the layer above the insulating layer, is formed by using a process such as plating, sputtering, CVD, vacuum evaporation or the like in combination with this. After the photosensitive insulating material that has been used as a mask becomes unnecessary, this material is removed. Wiring that connects the terminals in layers beneath the insulating layers and the terminals in layers above the insulating layers can be formed by means of the above processes.
For example, in semiconductor devices using the wafer level packaging technique, bonding pads consisting of aluminum or the like form the terminals in layers beneath the insulating layers, and bump pads form the terminals in layers above the insulating layers. Furthermore, such an insulating layer is formed on the surface of the semiconductor wafer in which semiconductor chips have been formed, and opening parts are formed in this insulating layer above the bonding pads. Moreover, metal wiring is formed from the bonding pads to the bump pads in the layer above the insulating layer. Bumps are formed on these bump pads. Furthermore, such formation of wiring from the bonding pads to the bump pads is called xe2x80x9cre-wiringxe2x80x9d. Moreover, the thickness of the insulating layer in this case is more or less equal to the thickness of the metal wiring.
Since the abovementioned processes are performed at one time on a plurality of semiconductor chips in a wafer state, this technique is characterized in that the cost of the assembly process can be reduced. Furthermore, the size of the respective semiconductor devices, after the devices have been split into individual units following the completion of the assembly process, is the same as the chip size (chip size packaging, CSP). Because of these two special features, the abovementioned process is referred to as xe2x80x9cwafer level chip size packagingxe2x80x9d, and the semiconductor devices formed by the abovementioned process are called xe2x80x9cwafer level chip size packagesxe2x80x9d. Furthermore, techniques that provide such wafer level chip size packages are sometimes called xe2x80x9cwafer level chip size packaging techniquesxe2x80x9d. Moreover, the terms xe2x80x9cwafer level chip size packagingxe2x80x9d, xe2x80x9cwafer level chip size packaging techniquesxe2x80x9d and xe2x80x9cwafer level chip size packagexe2x80x9d are all sometimes abbreviated to xe2x80x9cWLCSPxe2x80x9d.
One of the configurations whereby semiconductor devices manufactured by such a process are mounted and connected to a circuit board, such as a printed wiring board, is a flip-chip connection. Here, the connections between the semiconductor device and the circuit board are realized by a process in which the bumps formed on the bump pads of the semiconductor device are melted and then re-solidified on the circuit board. The gap between the semiconductor device and the circuit board is filled with a high-rigidity resin. Furthermore, this filling material, consisting of a high-rigidity resin, is called xe2x80x9cunderfillxe2x80x9d, and it has the effect of reinforcing the connection parts. Examples of flip-chip-connected semiconductor devices using such underfill are described in Japanese Patent Application Laid-Open No. H11-111768 and the like.
The following facts became clear as a result of an investigation of the abovementioned semiconductor devices and manufacturing methods, as conducted by the present inventor. Semiconductor devices are often shipped after being subjected to treatments in which the word-bit construction is altered, the width of the input-output bus is altered, or they are screened according to the operating speed of the semiconductor element. For example, in the case of memory elements, such as DRAM elements or the like, a method, such as the so-called bonding option or the like, in which the positions of the external connection terminals that are connected with the bonding wires are altered, may be employed in order to construct a semiconductor memory device with a wide bit width.
However, in the case of WLCSP of the type described above, a wire bonding technique is not used; accordingly, it is difficult to alter the positions of the pads connected with the individual re-wiring by means of such a method. For example, FIG. 18 is a schematic diagram of essential parts illustrating one example of the re-wiring structure in WLCSP. Here, a plurality of re-wiring lines 3, that electrically connect the bonding pads 1 and bump pads 2, are formed at one time by a photolithographic technique. Accordingly, in order to alter the connecting circuit of the bonding pads 1 and bump pads 2, it is necessary to alter the photomask used in the photolithographic process that forms the re-wiring lines 3; however, this creates problems in terms of time and cost, and prevents a flexible response.
Furthermore, in order to allow alteration of the connections between the bonding pads and bump pads in WLCSP of the type described above, it is also possible to incorporate a fuse circuit beforehand into the connection parts between the bonding pads and the bump pads, and to cut the fuses of this fuse circuit by means of a laser or the like, thus providing the performance required by the customer. In the case of this method, however, problems occur in terms of time and reliability, e.g., heat is generated when the fuses are cut by means of a laser, and an extra cutting process is required, so that such a method cannot be advantageously used.
Accordingly, it is an object of the present invention to provide a technique which makes it possible to respond flexibly to alterations in the connections of re-wiring in WLCSP. Moreover, it is an object of the present invention to provide a technique for obtaining semiconductor devices with the performance required by customers in a short time by accomplishing alterations in the connections of re-wiring in a simple and flexible manner.
Typical constituent elements of the invention disclosed in the present application may be briefly described as follows: specifically, the semiconductor device manufacturing method of the present invention comprises a step in WLCSP in which a wiring layer such as re-wiring is formed, wherein at least a portion of this wiring layer is formed using a photolithographic technique that does not use a photomask (i.e., that does not require a photomask), with one portion of this wiring layer being connected to first connection terminals, such as bonding pads, and with the remaining portion of-this wiring layer being connected to second connection terminals, such as bump pads. As a result, the combination of connections of these first connection terminals, such as bonding pads, and second connection terminals, such as bump pads, that are connected to each other by the wiring layer, such as re-wiring, can be simply and quickly rearranged, so that semiconductor devices that have the performance required by the customer can be provided in a short time.